1. Field
The disclosed embodiments relate to implementations of down counters. More specifically, the disclosed embodiments relate to asynchronous implementations of a loadable down counter.
2. Related Art
A loadable down counter is a circuit that can be loaded with any k-digit value N and then decrement exactly N times. This series of operations can then be repeated for different values of N. Loadable down counters are used often in hardware implementations to execute a certain set of operations N times, where the value of N may depend on user-provided information. Loadable down counters have been implemented as both synchronous and asynchronous circuits. For example, Joep Kessels describes an asynchronous implementation of a loadable down counter in “Designing Asynchronous Standby Circuits for a Low-Power Pager, J. Kessels and P. Marston, Proceedings of the IEEE, Special Issue on Asynchronous Circuits and Systems, Vol. 87, No. 2, February 1999. In this paper, Kessels specifies the down counter in the Tangram language, and the implementation comprises a translation of the specification into a handshake circuit. Unfortunately, these handshake circuits are slower, use greater area, and consume more power than other implementations.
Hence, what is needed are circuit implementations of a loadable down counter that are faster, use less area, and consume less power than previous implementations.